Microprocessor 8085 Lab Cycle:1 8 BIT-Addition/Subtraction/multiplication/Division Programs

 8 BIT DATA ADDITION

AIM:

             To add two 8 bit numbers stored at consecutive memory locations.

ALGORITHM:

1.      Initialize memory pointer to data location.

2.      Get the first number from memory in accumulator.

3.      Get the second number and add it to the accumulator.

4.      Store the answer at another memory location.

PROGRAM:

ADDRESS	OPCODE	LABEL	MNEMONICS	OPERAND	COMMENT
8000		START	MVI	C, 00	Clear C reg.
8001
8002			LXI	H, 9000	Initialize HL reg. to 9000
8003
8004
8005			MOV	A, M	Transfer first data to accumulator
8006			INX	H	Increment HL reg. to point next memory location.
8007			ADD	M	Add first number to acc. Content.
8008			JNC	L1	Jump to location if result does not yield carry.
8009
800A
800B			INR	C	Increment C reg.
800C		L1	INX	H	Increment HL reg. to point next memory location.
800D			MOV	M, A	Transfer the result from acc. to memory.
800E			INX	H	Increment HL reg. to point next memory location.
800F			MOV	M, C	Move carry to memory
8010			RST 5		Stop the program

OBSERVATION:

INPUT		OUTPUT
ADDRESS	DATA	ADDRESS	DATA
9000		9002
9001		9003

                

RESULT:

8 bit numbers stored at 9000 &9001 are added and the result stored at 9002 & 9003.

8 BIT DATA SUBTRACTION

AIM:

             To subtract two 8 bit numbers stored at consecutive memory locations.

ALGORITHM:

1.      Initialize memory pointer to data location.

2.      Get the first number from memory in accumulator.

3.      Get the second number and subtract from the accumulator.

4.      If the result yields a borrow,

a.       The content of the acc. is complemented and 01H is added to it (2’s complement).

b.      A register is cleared and the content of that reg. is incremented to store borrow.

5.      If there is no borrow the content of the acc. is directly taken as the result.

6.      Store the answer (in the accumulator and register) at next memory location.

RESULT:

Thus the 8 bit numbers stored at 9000 &9001 are subtracted and the result stored at 9002 & 9003.

PROGRAM:

ADDRESS	OPCODE	LABEL	MNEMONICS	OPERAND	COMMENT
8100		START	MVI	C, 00	Clear C reg.
8101
8102			LXI	H, 9000	Initialize HL reg. to 9000
8103
8104
8105			MOV	A, M	Transfer first data to accumulator
8106			INX	H	Increment HL reg. to point next  mem. Location.
8107			SUB	M	Subtract first number from acc. Content.
8108			JNC	L1	Jump to location if result does not yield borrow.
8109
810A
810B			INR	C	Increment C reg.
810C			CMA		Complement the Acc. content
810D			ADI	01H	Add 01H to content of  acc.
810E
810F		L1	INX	H	Increment HL reg. to point next mem. Location.
8110			MOV	M, A	Transfer the result from acc. to memory.
8111			INX	H	Increment HL reg. to point next mem. Location.
8112			MOV	M, C	Move carry to mem.
8113			RST 5		Stop the program

OBSERVATION:

INPUT		OUTPUT
ADDRESS	DATA	ADDRESS	DATA
9000		9002
9001		9003

8 BIT DATA MULTIPLICATION

AIM:

             To multiply two 8 bit numbers stored at consecutive memory locations and store the result in memory.

ALGORITHM:

LOGIC: Multiplication can be done by repeated addition.

1.      Initialize memory pointer to data location.

2.      Move multiplicand to a register.

3.      Move the multiplier to another register.

4.      Clear the accumulator.

5.      Add multiplicand to accumulator

6.      Decrement multiplier

7.      Repeat step 5 till multiplier comes to zero.

8.      The result, which is in the accumulator, is stored in a memory location.

RESULT:

Thus the 8-bit multiplication was done in 8085mp using repeated addition method.

PROGRAM:

ADDRESS	OPCODE	LABEL	MNEMONICS	OPERAND	COMMENT
8100		START	LXI	H, 9000	Initialize HL reg. to   9000
8101
8102					Transfer first data to reg. B
8103			MOV	B, M
8104			INX	H	Increment HL reg.  to point next memory location.
8105			MVI	A, 00H	Clear the acc.
8106
8107			MVI	C, 00H	Clear C register for carry
8108
8109		L1	ADD	M	Add multiplicand, multiplier times.
810A			JNC	NEXT	Jump to NEXT if there is no carry
810B
810C
810D			INR	C	Increment C register
810E		NEXT	DCR	B	Decrement B register
810F			JNZ	L1	Jump to L1 if B is not zero.
8110
8111
8112			INX	H	Increment HL reg. to point next memory location.
8113			MOV	M, A	Transfer the result from acc. to memory.
8114			INX	H	Increment HL reg. to point next memory location.
8115			MOV	M, C	Transfer the result from C reg. to  memory.
8116			RST 5		Stop the program

OBSERVATION:

INPUT		OUTPUT
ADDRESS	DATA	ADDRESS	DATA
9000		9002
9001		9003

 8 BIT DIVISION

AIM:

            To divide two 8-bit numbers and store the result in memory.

ALGORITHM:

LOGIC: Division is done using the method repeated subtraction.

1.      Load Divisor and Dividend

2.      Subtract divisor from dividend

3.      Count the number of times of subtraction which equals the quotient

4.      Stop subtraction when the dividend is less than the divisor .The dividend now becomes the remainder. Otherwise go to step 2.

5.      Stop the program execution.

RESULT:

            An ALP was written for 8-bit division using repeated subtraction method and executed using 8085m p kits

PROGRAM:

ADDRESS	OPCODE	LABEL	MNEMONICS	OPERAND	COMMENTS
8100			MVI	B,00	Clear B register for quotient
8101
8102			LXI	H,9000	Initialize HL reg. to 9000H
8103
8104
8105			MOV	A,M	Transfer dividend to acc.
8106			INX	H	Increment HL reg.  to point next memory location.
8107		LOOP	SUB	M	Subtract divisor from dividend
8108			INR	B	Increment B register
8109			JNC	LOOP	Jump to LOOP  if result does not yield borrow
810A
810B
810C			ADD	M	Add divisor to acc.
810D			DCR	B	Decrement B register
810E			INX	H	Increment HL reg. to point next memory location.
810F			MOV	M,A	Transfer the remainder from acc. to memory.
8110			INX	H	Increment HL reg. to point next memory location.
8111			MOV	M,B	Transfer the quotient from B reg. to memory.
8112			RST 5		Stop the program

OBSERVATION:

INPUT		OUTPUT
ADDRESS	DATA	ADDRESS	DATA
9000		9002
9001		9003

8251 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) Notes

8251 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART)

The 8251 is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serial data communication. As a peripheral device of a microcomputer system, the 8251 receives parallel data from the CPU and transmits serial data after conversion. This device also receives serial data from the outside and transmits parallel data to the CPU after conversion.

Block diagram of the 8251 USART (Universal Synchronous Asynchronous Receiver Transmitter)

The 8251 functional configuration is programed by software. Operation between the 8251 and a CPU is executed by program control. Table 1 shows the operation between a CPU and the device.

Table 1 Operation between a CPU and 8251

Control Words

There are two types of control word.

1. Mode instruction (setting of function)

2. Command (setting of operation)

1) Mode Instruction

Mode instruction is used for setting the function of the 8251. Mode instruction will be in "wait for write" at either internal reset or external reset. That is, the writing of a control word after resetting will be recognized as a "mode instruction."

Items set by mode instruction are as follows:

• Synchronous/asynchronous mode

• Stop bit length (asynchronous mode)

• Character length

• Parity bit

• Baud rate factor (asynchronous mode)

• Internal/external synchronization (synchronous mode)

• Number of synchronous characters (Synchronous mode)

The bit configuration of mode instruction is shown in Figures 2 and 3. In the case of synchronous mode, it is necessary to write one-or two byte sync characters. If sync characters were written, a function will be set because the writing of sync characters constitutes part of mode instruction.

2) Command

Command is used for setting the operation of the 8251. It is possible to write a command whenever necessary after writing a mode instruction and sync characters.

Items to be set by command are as follows:

• Transmit Enable/Disable

• Receive Enable/Disable

• DTR, RTS Output of data.

• Resetting of error flag.

• Sending to break characters

• Internal resetting

• Hunt mode (synchronous mode)

Status Word

It is possible to see the internal status of the 8251 by reading a status word. The bit configuration of status word is shown in Fig. 5.

Pin Description

D 0 to D 7 (l/O terminal)

This is bidirectional data bus which receive control words and transmits data from the CPU and sends status words and received data to CPU.

RESET (Input terminal)

A "High" on this input forces the 8251 into "reset status." The device waits for the writing of "mode instruction." The min. reset width is six clock inputs during the operating status of CLK.

CLK (Input terminal)

CLK signal is used to generate internal device timing. CLK signal is independent of RXC or TXC. However, the frequency of CLK must be greater than 30 times the RXC and TXC at Synchronous mode and Asynchronous "x1" mode, and must be greater than 5 times at Asynchronous "x16" and "x64" mode.

WR (Input terminal)

This is the "active low" input terminal which receives a signal for writing transmit data and control words from the CPU into the 8251.

RD (Input terminal)

This is the "active low" input terminal which receives a signal for reading receive data and status words from the 8251.

C/D (Input terminal)

This is an input terminal which receives a signal for selecting data or command words and status words when the 8251 is accessed by the CPU. If C/D = low, data will be accessed. If C/D = high, command word or status word will be accessed.

CS (Input terminal)

This is the "active low" input terminal which selects the 8251 at low level when the CPU accesses. Note: The device won’t be in "standby status"; only setting CS = High.

TXD (output terminal)

This is an output terminal for transmitting data from which serial-converted data is sent out. The device is in "mark status" (high level) after resetting or during a status when transmit is disabled. It is also possible to set the device in "break status" (low level) by a command.

TXRDY (output terminal)

This is an output terminal which indicates that the 8251is ready to accept a transmitted data character. But the terminal is always at low level if CTS = high or the device was set in "TX disable status" by a command. Note: TXRDY status word indicates that transmit data character is receivable, regardless of CTS or command. If the CPU writes a data character, TXRDY will be reset by the leading edge or WR signal.

TXEMPTY (Output terminal)

This is an output terminal which indicates that the 8251 has transmitted all the characters and had no data character. In "synchronous mode," the terminal is at high level, if transmit data characters are no longer remaining and sync characters are automatically transmitted. If the CPU writes a data character, TXEMPTY will be reset by the leading edge of WR signal. Note : As the transmitter is disabled by setting CTS "High" or command, data written before disable will be sent out. Then TXD and TXEMPTY will be "High". Even if a data is written after disable, that data is not sent out and TXE will be "High".After the transmitter is enabled, it sent out. (Refer to Timing Chart of Transmitter Control and Flag Timing)

TXC (Input terminal)

This is a clock input signal which determines the transfer speed of transmitted data. In "synchronous mode," the baud rate will be the same as the frequency of TXC. In "asynchronous mode", it is possible to select the baud rate factor by mode instruction. It can be 1, 1/16 or 1/64 the TXC. The falling edge of TXC sifts the serial data out of the 8251.

RXD (input terminal)

This is a terminal which receives serial data.

RXRDY (Output terminal)

This is a terminal which indicates that the 8251 contains a character that is ready to READ. If the CPU reads a data character, RXRDY will be reset by the leading edge of RD signal. Unless the CPU reads a data character before the next one is received completely, the preceding data will be lost. In such a case, an overrun error flag status word will be set.

RXC (Input terminal)

This is a clock input signal which determines the transfer speed of received data. In "synchronous mode," the baud rate is the same as the frequency of RXC. In "asynchronous mode," it is possible to select the baud rate factor by mode instruction. It can be 1, 1/16, 1/64 the RXC.

SYNDET/BD (Input or output terminal)

This is a terminal whose function changes according to mode. In "internal synchronous mode." this terminal is at high level, if sync characters are received and synchronized. If a status word is read, the terminal will be reset. In "external synchronous mode, "this is an input terminal. A "High" on this input forces the 8251 to start receiving data characters.

In "asynchronous mode," this is an output terminal which generates "high level"output upon the detection of a "break" character if receiver data contains a "low-level" space between the stop bits of two continuous characters. The terminal will be reset, if RXD is at high level. After Reset is active, the terminal will be output at low level.

DSR (Input terminal)

This is an input port for MODEM interface. The input status of the terminal can be recognized by the CPU reading status words.

DTR (Output terminal)

This is an output port for MODEM interface. It is possible to set the status of DTR by a command.

CTS (Input terminal)

This is an input terminal for MODEM interface which is used for controlling a transmit circuit. The terminal controls data transmission if the device is set in "TX Enable" status by a command. Data is transmitable if the terminal is at low level.

RTS (Output terminal)

This is an output port for MODEM interface. It is possible to set the status RTS by a command.

Programmable Peripheral/Parallel Interface Notes-PPI-8255

The 8255 is a widely used, programmable, parallel I/O device.

• It can be programmed to transfer data under various conditions, from simple I/O to interrupt I/O. 
• It is flexible, versatile and economical and complex. 

The 8255 has 24 I/O pins that can be grouped primarily into two 8 bit parallel ports: A and B, with the remaining 8 bits a port C. The 8 bits of port C can be used as individual bits or be grouped in two 4-bit ports: CUPPER (CU) and CLOWER (CL), as shown in the figure 1.1. The functions of these ports are defined by writing a control word in the control register.

Figure 1.2 shows all the functions of 8255; classified according to two modes: the Bit Set/Reset (BSR) mode and I/O mode. The BSR mode is used to set or reset the bits in port C. The I/O mode is further divided into three modes: Mode 0, Mode 1 and Mode 2. In Mode 0, all ports function as simple I/O ports. Mode 1 is a hand shake mode whereby Ports A and/or B use bits from port C ashandshake signals. In Mode 2 Port A can be set up for bidirectional data transfer using handshaking signals from Port C, and Port B can be set up either in Mode 0 or Mode 1.

Block Diagram of the 8255

CONTROL LOGIC

(Read): This control signal enables the Read operation. When the signal is low, the MPU reads data fro a selected I/O Port of the 8255.

(Write): This control signal enables the write operation. When the signal goes low, MPU writes into a selected I/O Port or control register.

RESET     (Reset): This is an active high signal; it clears the control register and sets all ports in the input      mode.

, A0 and A1: Theses are device select signals. Chip Select is connected to a decoded address, and A0 and A1 are generally connected to MPU address lines A0 and A1 respectively 

CONTROL WORD

Figure 1.5 shows a register called the control register. The contents of this register called control word. This register can be accessed to write a control word when A0 and A1 are at logic 1. This control register is not accessible for a read operation.

     Bit D7 of the control register specifies either I/O function or the Bit Set/Reset function. If bit D7=1, bits D6-D0 determines I/O functions in various modes. If bit D7=0, Port C operates in the Bit Set/Reset (BSR) mode. The BSR control word does not affect the functions of Port A and Port B.

To communicate with peripherals through the 8255, three steps are necessary:


1. Determine the address of ports A, B and C and of the control register according to the chip select logic and address lines A0 andA1.

2. Write the control word in the control register.

3. Write I/O instructions to communicate with peripherals through Ports A, B and C.

Operating Modes 
  
Mode 0: Simple Input or Output

In this mode, ports A, B are used as two simple 8-bit I/O ports and port C as two 4-bit ports. Each port can be programmed to function as simply an input port or an output port. The input/output features in Mode 0 are as follows.

1. Outputs are latched.

2. Inputs are not latched.

3. Ports don’t have handshake or interrupt capability.

Mode 1: Input or Output with Handshake 
  
In this mode, handshake signals are exchanged between the MPU and peripherals prior to data transfer. The features of the mode include the following: 


1. Two ports (A and B) function as 8-bit I/O ports. They can be configured as either as input or output ports.

2. Each port uses three lines from ort C as handshake signals. The remaining two lines of Port C can be used for simple I/O operations.

3. Input and Output data are latched.

4. Interrupt logic is supported.

Mode 2: Bidirectional Data Transfer 

This mode is used primarily in applications such as data transfer between two computers. In this mode, Port A can be configured as the bidirectional port and Port B either in Mode 0 or Mode 1. Port A uses five signals from Port C as handshake signals for data transfer. The remaining three signals from port C can be used either as simple I/O or as handshake for port B.

BSR (Bit Set/Reset) Mode

The BSR mode is concerned only with the eight bits of port C, which can be set or reset by writing an appropriate control word in the control register. A control word with bit D7 =0 is recognized as a BSR control word, and it does not alter any previously transmitted control word with bit D7=1; thus the I/O operations of ports A and B are not affected by a BSR control word. In BSR mode, individualbits of port C can be used for applications such as an on/off switch. Ports A and B are not affected by the BSR Mode.

BSR CONTROL WORD


This control word, when written in the control register, sets or resets one bit at a time,

source:Lectnotes