Microprocessor 8086 Notes-UNIT-4

Unit-4

Microprocessor

Features of 8086

The most prominent features of a 8086 microprocessor are as follows −

·         It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal data bus, and 16-bit external data bus resulting in faster processing.

·         It is available in 3 versions based on the frequency of operation −

1. 8086 → 5MHz
2. 8086-2 → 8MHz
3. 8086-1 → 10 MHz

·         It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which improves performance.

·         It has a powerful instruction queue, which helps in storing of six instruction bytes from the memory. This indicates in faster processing.

·         Fetch stage can pre fetch up to 6 bytes of instructions and stores them in the queue.

·         Execute stage executes these stored instructions.

·         It has 256 vectored interrupts.

·         It consists of 29,000 transistors.

·          

1. Explain the Architecture/ functional units of 8086 Microprocessor?

8086 Microprocessor is provided with two functional units, i.e., EU (Execution Unit) and BIU (Bus Interface Unit).

EU (Execution Unit)

Execution unit is a functional unit consists of CPU which helps in performing operations and arithmetical calculations instructed by the computer program. In machine language we could say that it decodes and executes instructions. Apart from other internal units it has its own control unit which helps to perform functions along with other basic internal units. The data which is required by the EU is fetched from the BIU thus maintaining interaction with the memory and input and output devices.

Let us now discuss the functional parts of 8086 microprocessors.

ALU

As we know ALU handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT operations.

Flag Register

Flag Register is a 16-bit register that looks like a flip-flop, i.e. with the result of data that is stored in the accumulator its status changes. It consists of 9 flags and they are divided into 2 groups − Conditional Flags and Control Flags.

Conditional Flags

It is determined with the result of the execution by the last arithmetic or logical instruction. Following is the list of conditional flags −

·         Carry flag − This flag indicates an overflow condition for arithmetic operations.

·         Auxiliary flag − When an operation is processed at ALU, it results in a carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), then this flag is set, i.e. carry given by D3 bit to D4 is AF flag. The processor uses this flag to perform binary to BCD conversion.

·         Parity flag − This flag is used to indicate result of even and odd number sets of the parity, i.e. when the lower order 8-bits of the result contains even number of 1’s, then the Parity Flag is set. When the odd number of 1’s contains, the Parity Flag is reset.

·         Zero flag − This flag is set to 1 when the result of arithmetic or logical operation is said to be zero else it is set to 0.

·         Sign flag − This flag holds the sign of the result, i.e. when the result of the operation is negative, then the sign flag is set to 1 otherwise set to 0.

·         Overflow flag − This flag represents the result when the system capacity is exceeded.

Control Flags

Control flags controls the operations performed by the execution unit. Following is the list of control flags −

·         Trap flag − It is a single step process control that allows the user to execute single instruction at a time for debugging. If it is set, then the program could run in a single step mode.

·         Interrupt flag − It is an interrupt enable/disable flag, i.e. helps to allow/prohibit the interruption of a program. For interrupt enabled condition it is set to 1 and for interrupt disabled condition it is set to 0.

·         Direction flag − It is used in string operation, where the string bytes are set and accessed from the higher memory address to the lower memory address and vice-a-versa.

General purpose register

There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL. These registers can be used individually when it is stored in 8-bit data and 16bit data is required to store in pairs. The valid register pairs are AH and AL, BH and BL, CH and CL, and DH and DL. It is referred to the AX, BX, CX, and DX respectively.

·         AX register − It is also known as accumulator register. It is used to store operands to perform arithmetic operations.

·         BX register − It is used as a base register. It is used to store the initial base address of the memory area within the data segment.

·         CX register − It is referred to as counter. It is used in loop instruction to store the loop counter.

·         DX register − This is a register which is used to hold I/O port address for I/O instruction.

Stack pointer register

It is known as a 16-bit register, which handles the last program address that was recently stored on the stack to the memory location.

BIU (Bus Interface Unit)

To increase the processing speed of the processor 8086 microprocessor has been divided into EU and BIU functional units. As we have mentioned above that the EU codes and decodes the data, BIU interacts with the memory, input and output devices in order to fetch the instructions and data thereby transfer of all data and addresses on the buses for the EU execution. This unit helps in sending addresses, fetching instructions from the memory, reading data from the ports and the memory as well as writing data to the ports and the memory. EU does not have any direct connection with System Buses so this is possible with the BIU. Fetching and execution works simultaneously to increase the performance of the microprocessor.

It has the following functional parts −

·         Instruction queue − BIU consists of the instruction queue. BIU holds upto 6 bytes of next executable instructions and stores them in the instruction queue. When execution of instructions happens by the EU and gets ready for its next instruction, then it simply reads the instruction from this instruction queue which results in increased performance of the microprocessor.

·         Execution of current instruction while the next instruction is being fetched is called pipelining.

·         Segment register − BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the addresses of instructions and data in memory, which are later used by the processor in order to access memory locations. It also contains 1 pointer register IP, which holds the address of the next instruction that is executed by the EU.

o    CS − It stands for Code Segment used for addressing a memory location in the code segment of the memory, where the program ready to execute is to be stored.

o    DS − It stands for Data Segment. It contains data used by the program and is accessed in the data segment by an offset address i.e logical address or the content of other register that holds the offset address. Execution unit is responsible for offset address as it executes the program.

o    SS − It stands for Stack Segment. It holds memory to store data which helps in addressing during execution.

o    ES − It stands for Extra Segment. ES is additional data segment, which is used by the string to hold the extra processed destination data.

·         Instruction pointer − It is known as 16-bit register which handles the address of the immediate next executable instruction.

2. Explain in detail the Pin structure of 8086 Microprocessor

Power supply and frequency signals

It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its operation.

Clock signal

Clock signal is provided through Pin-19. It gives timing to the processor to perform operations. It has different frequency for different versions, i.e. 5MHz, 8MHz and 10MHz.

Address/data bus

AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte data and AD8AD15 carries higher order byte data. During the first clock cycle of operation, it carries 16-bit address and after that it carries 16-bit data.

Address/status bus

A16-A19/S3-S6. These are the 4 address/status buses. While the first clock cycle is running, it carries 4-bit address and later it carries status signals.

S7/BHE

BHE stands for Bus High Enable. It is available at pin 34 and helps in recognizing transfer of data using data bus D8-D15. during first clock cycle it becomes low and later it becomes active.

Read($\overline{RD}$)

It is available at pin 32 and is used to read signal for Read operation.

Ready

It is available at pin 32. The data that is transferred fromt he I/O devices is provided by an acknowledgement signal.. It is an active high signal. When it is high, it gives signals that the device is ready to transfer data. When it is low, it indicates that the device is not ready and should give a pause for some time.

RESET

It is available at pin 21 and is used to repeat the execution. Its present activity is immediately terminated by the processor. This signal will be active high for the first 4 clock cycles to RESET the microprocessor.

INTR

It is available at pin 18. It is considered as an interrupt request signal, which is sampled during the last clock cycle of each instruction in order to determine whether the processor is considering as an interrupt or not.

NMI

It stands for non-maskable interrupt and is available at pin 17. It is known as an edge triggered input, which specifies an interrupt request to the microprocessor.

$\overline{TEST}$

This signal is like wait state and is available at pin 23. When this signal is raised high, then the processor has to wait for IDLE state, otherwise the execution continues.

MN/$\overline{MX}$

It stands for Minimum/Maximum and is available at pin 33. It indicates as to which mode the processor has to operate.; when it is high, it works in the minimum mode and vice-a-versa( the process continues).

INTA

It is available at pin 24 which is provided by an interrupt acknowledgement signal . When the microprocessor receives this signal, it acknowledges the interrupt.

ALE

It stands for address enable latch which is available at pin 25. If any operation is performed by the processor everytime a positive pulse is produced. This signal indicates the availability of a valid address on the address/data lines.

DEN

It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver 8286. The transreceiver is a device which is used to separate data from the address/data bus.

DT/R

It stands for Data Transmit/Receive signal and is available at pin 27. It decides flow of data direction through the transreceiver. When it is high, data is transmitted out and vice-a-versa.

M/IO

This signal is used to differentiate between memory and I/O operations. When it is high, it indicates I/O operation and when it is low indicates the memory operation. It is available at pin 28.

WR

It stands for write signal and is available at pin 29. As the name indicates it is used to write the data into the memory or the output device based on the status of M/IO signal.

HLDA

It stands for Hold Acknowledgement signal and is available at pin 30. This signal acknowledges the HOLD signal.

HOLD

This signal gives hints to the processor that external devices are requesting to access the address/data buses. It is available at pin 31.

QS1 and QS0

These are queue status signals and are available at pin 24 and 25. These signals provide the status of instruction queue. Their conditions are shown in the following table −

QS0	QS1	Status
0	0	No operation
0	1	First byte of opcode from the queue
1	0	Empty the queue
1	1	Subsequent byte from the queue

S0, S1, S2

These are the status signals that provide the status of operation, which is used by the Bus Controller 8288 to produce memory & I/O control signals. These are available at pin 26, 27, and 28. Following is the table showing their status −

S2	S1	S0	Status
0	0	0	Interrupt acknowledgement
0	0	1	I/O Read
0	1	0	I/O Write
0	1	1	Halt
1	0	0	Opcode fetch
1	0	1	Memory read
1	1	0	Memory write
1	1	1	Passive

LOCK

Actually it is available at pin 29 where activation is done with the use of LOCK prefix on any instruction. When this signal is active, it raises alarm to the other processors not to ask the CPU to leave the system bus. It becomes active using the LOCK prefix on any instruction and is available at pin 29.

RQ/GT1 and RQ/GT0

These are the Request/Grant signals used by other processors to send the request to the CPU to release the system bus. When the signal is received by CPU, it sends acknowledgment. RQ/GT0 has a higher priority than RQ/GT1.

3. What is Segmentation and list its advantages? Explain about segment registers in 8086 and about their default offset registers?

Segmentation is the process in which the main memory of the computer is divided into different segments and each segment has its own base address. It is basically used to enhance the speed of execution of the computer system, so that processor is able to fetch and execute the data from the memory easily and fast.

Need for Segmentation –
The Bus Interface Unit (BIU) contains four 16 bit special purpose registers (mentioned below) called as Segment Registers.

·         Code segment register (CS): is used for addressing memory location in the code segment of the memory, where the executable program is stored.

·         Data segment register (DS): points to the data segment of the memory where the data is stored.

·         Extra Segment Register (ES): also refers to a segment in the memory which is another data segment in the memory.

·         Stack Segment Register (SS): is used for addressing stack segment of the memory. The stack segment is that segment of memory which is used to store stack data.

The number of address lines in 8086 is 20, 8086 BIU will send 20bit address, so as to access one of the 1MB memory locations. The four segment registers actually contain the upper 16 bits of the starting addresses of the four memory segments of 64 KB each with which the 8086 is working at that instant of time. A segment is a logical unit of memory that may be up to 64 kilobytes long. Each segment is made up of contiguous memory locations. It is independent, separately addressable unit. Starting address will always be changing. It will not be fixed.

Note that the 8086 does not work the whole 1MB memory at any given time. However it works only with four 64KB segments within the whole 1MB memory.

Bellow is the one way of positioning four 64 kilobyte segments within the 1M byte memory space of an 8086.

Advantages of the Segmentation The main advantages of segmentation are as follows:

·         It provides a powerful memory management mechanism.

·         Data related or stack related operations can be performed in different segments.

·         Code related operation can be done in separate code segments.

·         It allows to processes to easily share data.

·         It allows to extend the address ability of the processor, i.e. segmentation allows the use of 16 bit registers to give an addressing capability of 1 Megabytes. Without segmentation, it would require 20 bit registers.

·         It is possible to enhance the memory size of code data or stack segments beyond 64 KB by allotting more than one segment for each area.

Effective Address= Segment Register *10+offset

Eg: In 8086 processor the code segment contains 4000H and instruction pointer contains 9F20H. Find the effective address or memory location addressed by the processor.

∴The Calculated Physical address = 49F20H

 

4. Explain in Detail Various Addressing Modes of 8086:

The way of specifying data to be operated by an instruction is known as addressing modes.

1.             Immediate: In this type of addressing, immediate data is a part of instruction, and appears in the form of successive byte or bytes.

Example: MOV AX, 0005H

In the above example, 0005H is the immediate data. The immediate data may be 8-bit or 16-bit in size.

2.             Direct: In the direct addressing mode, a 16-bit memory address (offset) is directly specified in the instruction as a part of it.

Example: MOV AX, [5000H]

Here, data resides in a memory location in the data segment, whose effective address may be computed using 5000H as the offset address and content of DS as segment address. The effective address, here, is 10H*DS+5000H.

3.             Register: In register addressing mode, the data is stored in a register and it is referred using the particular register. All the registers, except IP, may be used in this mode.

Example: MOV BX, AX.

4.             Register Indirect: Sometimes, the address of the memory location, which contains data or operand, is determined in an indirect way, using the offset registers. This mode of addressing is known as register indirect mode. In this addressing mode, the offset address of data is in either BX or SI or DI registers. The default segment is either DS or ES. The data is supposed to be available at the address pointed to by the content of any of the above registers in the default data segment.

Example: MOV AX, [BX]

Here, data is present in a memory location in DS whose offset address is in BX. The effective address of the data is given as 10H*DS+ [BX].

5.             Indexed: In this addressing mode, offset of the operand is stored in one of the index registers. DS and ES are the default segments for index registers SI and DI respectively. This mode is a special case of the above discussed register indirect addressing mode.

Example: MOV AX, [SI]

Here, data is available at an offset address stored in SI in DS. The effective address, in this case, is computed as 10H*DS+ [SI].

6.             Register Relative: In this addressing mode, the data is available at an effective address formed by adding an 8-bit or 16-bit displacement with the content of any one of the registers BX, BP, SI and DI in the default (either DS or ES) segment. The example given before explains this mode.

       Example: MOV Ax, 50H [BX]

       Here, effective address is given as 10H*DS+50H+ [BX].

7.             Based Indexed: The effective address of data is formed, in this addressing mode, by adding content of a base register (any one of BX or BP) to the content of an index register (any one of SI or DI). The default segment register may be ES or DS.

Example: MOV AX, [BX] [SI]

Here, BX is the base register and SI is the index register. The effective address is computed as 10H*DS+ [BX] + [SI].

8.             Relative Based Indexed: The effective address is formed by adding an 8-bit or 16-bit displacement with the sum of contents of any one of the bases registers (BX or BP) and any one of the index registers, in a default segment.

Example: MOV AX, 50H [BX] [SI]

Here, 50H is an immediate displacement, BX is a base register and SI is an index register. The effective address of data is computed as 160H*DS+ [BX] + [SI] + 50H.