Interrupt
of 8085
An interrupt is a signal from a device
attached to a microprocessor or from a program within the processor that causes
the main program to stop and figure out what to do next. (Or) Interrupt is a
process where an external device can get the attention of the microprocessor.
What
happens when MP is interrupted ?
•
When
the Microprocessor receives an interrupt signal, it suspends the currently
executing program and jumps to an Interrupt Service Routine (ISR) to respond to
the incoming interrupt. Each interrupt will most probably have its own ISR. There
are two ways of redirecting the execution to the ISR depending on whether the
interrupt is vectored or non-vectored.
–
Vectored: The address of the subroutine is
already known to the Microprocessor
–
Non Vectored: The device will have to supply the
address of the subroutine to the Microprocessor
•
When
a device interrupts, it actually wants the MP to give a service which is
equivalent to asking the MP to call a subroutine. This subroutine is called ISR (Interrupt Service Routine) The
‘EI’ instruction is a one byte instruction and is used to Enable the
non-maskable interrupts.The ‘DI’ instruction is a one byte instruction and is
used to Disable the non-maskable interrupts.
Classification
of Interrupts
1.Hardware Interrupts (TRAP, RST7.5, RST
6.5, RST5.5 and INTR)
2.Software Interrupts (RST0, RST1, RST2, RST3, RST4, RST5, RST6,
RST7)
Hardware
Interrupts:An external device initiates the
hardware interrupts and placing an appropriate signal at the interrupt pin of
the processor. If the interrupt is accepted then the processor executes an
interrupt service routine. The 8085 has five hardware interrupts
(1)
TRAP (2) RST 7.5 (3) RST 6.5 (4) RST 5.5 (5) INTR
Classification
of Interrupts
1.
Maskable
and Non Maskable
2.
Vectored
and Non vectored
3.
Edge
triggered and Level Triggered
4.
Priority
Based Interrupts
1.Maskable
interrupts :Maskable
interrupts are those interrupts which can be enabled or disabled.Enabling and
Disabling is done by software instructionsRST7.5, RST 6.5, RST5.5 and INTR. Non-maskable
interrupts.:The interrupts
which are always in enabled mode are called non-maskable interrupts.These
interrupts can never be disabled by any
software instructions.TRAP is non-maskable interrupt
2.Vectored
Interrupts:The
vectored Interrupts points to the particular location in memory.List of
vectored Interrupts TRAP, RST7.5, RST 6.5, RST5.5
Non
vectored Interrupts:The
Interrupts which don’t have fixed memory location for transfer of control from
normal execution. INTR is a Non
vectored Interrupt
3.Edge
triggered Interrupt:The
interrupts which are triggered at leading or trailing edge are called edge
triggered Interrupt.RST7.5 is a Edge triggered Interrupt.Level Triggered Interrupt:The
interrupts which are triggered at high or low level are called Level
Triggered Interrupt.RST 6.5, RST5.5 and
INTR is a Level Triggered Interrupt
4.Priority
Based Interrupts:Whenever
there exists a simultaneous request at two or more pins then the pin with
higher priority is selected by the microprocessor
Comparison
of hardware Interrupts
The 8085 Non-Vectored Interrupt Process
- The interrupt process should be enabled using the EI instruction.
- The 8085 checks for an interrupt during the execution of every instruction.
- If INTR is high, MP completes current instruction, disables the interrupt and sends INTA (Interrupt acknowledge) signal to the device that interrupted
- INTA allows the I/O device to send a RST instruction through data bus.
- Upon receiving the INTA signal, MP saves the memory location of the next instruction on the stack and the program is transferred to ‘call’ location (ISR Call) specified by the RST instruction
- Microprocessor Performs the ISR.
- ISR must include the ‘EI’ instruction to enable the further interrupt within the program.
- RET instruction at the end of the ISR allows the MP to retrieve the return address from the stack and the program is transferred back to where the program was interrupted.
Software Interrupt:
•
The
8085 recognizes 8 RESTART instructions: RST0 - RST7.Each of these would send
the execution to a predetermined hard-wired memory location:
|
Restart
Instruction
|
Equivalent to
|
|
RST0
|
CALL 0000H
|
|
RST1
|
CALL 0008H
|
|
RST2
|
CALL 0010H
|
|
RST3
|
CALL 0018H
|
|
RST4
|
CALL 0020H
|
|
RST5
|
CALL 0028H
|
|
RST6
|
CALL 0030H
|
|
RST7
|
CALL 0038H
|
The restart
sequence is made up of three machine cycles
–
In
the 1st machine cycle:
•
The
microprocessor sends the INTA signal.
•
While
INTA is active the microprocessor reads the data lines expecting to receive,
from the interrupting device, the opcode for the specific RST instruction.
–
In
the 2nd and 3rd machine cycles:
•
the
16-bit address of the next instruction is saved on the stack.
•
Then
the microprocessor jumps to the address associated with the specified RST
instruction.
