Dr.Sirisha Daggubati's Engineering Study Material: October 2012

Friday 26 October 2012

Computer Architecture-OBJECTIVE TYPE 75 QUESTIONS-Gate

Computer Architecture

PART - I

OBJECTIVE TYPE QUESTIONS

Choose correct or the best alternative in the following:

Q.1 In a virtual memory system, the addresses used by the programmer belongs to

(A) memory space. (B) physical addresses.

Ans: C

An address used by programmers in a system supporting virtual memory concept is

called virtual address and the set of such addresses are called address space.

Q.2 The method for updating the main memory as soon as a word is removed from the

Cache is called

(A) Write-through (B) write-back

Ans: B

In this method only cache location is updated during write operation.

Q.3 A control character is sent at the beginning as well as at the end of each block in the

synchronous-transmission in order to

(A) Synchronize the clock of transmitter and receiver.

(B) Supply information needed to separate the incoming bits into individual

character.

(D) Both (A) and (C).

Ans B

As the data are sent continuously as a block of data at the rate dictated by the clock

frequency, so the receiver should be supplied with the same function about the same

bit length in order to interrupt the information.

Q.4 In a non-vectored interrupt, the address of interrupt service routine is

(A) Obtained from interrupt address table.

(B) Supplied by the interrupting I/O device.

(D) Assigned to a fixed memory location.

Ans: D

The source device that interrupted the processor supply the vector address which

helps processor to find out the actual memory location where ISR is stored for the

device.

Q.5 Divide overflow is generated when

(A) Sign of the dividend is different from that of divisor.

(B) Sign of the dividend is same as that of divisor.

Ans: B

If the first part of the dividend is greater than the deviser, then the result should be

of greater length, then that can be hold in a register of the system. The registers are

of fixed length in

any processor.

Q.6 Which method is used for resolving data dependency conflict by the compiler

itself?

(A) Delayed load. (B) operand forwarding.

Ans: A

In case of delayed load technique the complier detects the data conflict and reorder

the instruction as necessary to delay the loading of the conflicting data by inserting

no operation instructions.

Q.7 Stack overflow causes

(A) Hardware interrupt.

(B) External interrupt.

(D) Software interrupt.

Ans: C

Stack overflow occurs while execution of a program due to logical faults. So it is a

program dependent, hence interrupt activated.

Q.8 Arithmetic shift left operation

(A) Produces the same result as obtained with logical shift left operation.

(B) Causes the sign bit to remain always unchanged.

(D) Is not applicable for signed 2's complement representation.

Ans: A

If the register hold minus five in two’s compliment form than in arithmetic shift left

the contents of the register shall be

It is found that the register contents multiplied by two after logical shift left

operation. Hence arithmetic shift left operation is same as logical shift operation.

Q.9 Zero address instruction format is used for

(A) RISC architecture.

(B) CISC architecture.

(D) Stack-organized architecture.

Ans: D

In stack organized architecture push and pop instruction is needs a address field to

specify the location of data for pushing into the stack and destination location

during pop operation but for logic and arithmetic operation the instruction does not

need any address field as it operates on the top two data available in the stack.

Q.10 Address symbol table is generated by the

(A) memory management software.

(B) assembler.

(D) generated by operating system

Ans: B

During the first pass of assembler address symbol table is generated which contains

the label used by the programmer and its actual address with reference to the stored

program.

Q.11 The ASCII code for letter A is

(A) 1100011 (B) 1000001

Ans. (B)

Q.12 The simplified expression of (A+B) + C is

(A) (A + B)C (B) A(B + C)

Ans. (A)

Q.13 The negative numbers in the binary system can be represented by

(A) Sign magnitude (B) I's complement

Ans. (C)

Q.14 ABCD - seven segment decoder / driver in connected to an LED display.

Which segments are illuminated for the input code DCBA = 0001.

(A)b, c (B) c, b

(C)a, b, c (D) a, b, c, d

Ans. (A)

Q.15 How many flip-flops are required to produce a divide-by-32 device?

(A)4 (B) 6

Ans. (C)

Q.16 The content of a 4-bit register is initially 1101. The register is shifted 2 times to

the right with the serial input being 1011101.

What is the content of the register after each shift?

(A)1110, 0111 (B) 0001, 1000

Ans. (A)

Q.17 How many different addresses are required by the memory that contain 16K

words?

(A)16,380 (B) 16,382

Ans. (C)

Q.18 What is the bit storage capacity of a ROM with a 512' 4-organization?

(A) 2049 (B) 2048

Ans. (B)

Q.19 DMA interface unit eliminates the need to use CPU registers to transfer data

from

(A) MAR to MBR (B) MBR to MAR

Ans. (D)

Q.20 How many 128 x 8 RAM chips are needed to provide a memory capacity of

2048 bytes?

(A) 8 (B) 16

Ans. (B)

Q.21 Which of the following is a self complementing code?

(A) 8421 code (B) 5211

Ans. (A)

Q.22 Which gate can be used as anti-coincidence detector?

(A) X-NOR (B) NAND

Ans. (C)

Q.23 Which of the following technology can give high speed RAM?

(A) TTL (B) CMOS

Ans. (C)

Q.24 In 8085 microprocessor how many I/O devices can be interfaced in I/O mapped

I/O technique?

(A) Either 256 input devices or 256 output devices.

(B) 256 I/O devices.

(D) 512 input-output devices.

Ans. (C)

Q.25 After reset, CPU begins execution of instruction from memory address

(A) 0101H (B) 8000H

Ans. (C)

Q.26 Which is true for a typical RISC architecture?

(A) Micro programmed control unit.

(B) Instruction takes multiple clock cycles.

(D) Emphasis on optimizing instruction pipelines.

Ans. (A)

Q.27 When an instruction is read from the memory, it is called

(A) Memory Read cycle (B) Fetch cycle

Ans. (B)

Q.28 Which activity does not take place during execution cycle?

(A) ALU performs the arithmetic & logical operation.

(B) Effective address is calculated.

(D) Branch address is calculated & Branching conditions are

checked.

Ans. (D)

Q.29 A circuit in which connections to both AND and OR arrays can be

programmed is called

(A) RAM (B) ROM

Ans. (A)

Q.30 If a register containing data (11001100)2 is subjected to arithmetic shift left

operation, then the content of the register after 'ashl' shall be

(A) (11001100)2 (B) (1101100)2

Ans. (D)

Q.31 Which logic is known as universal logic?

(A) PAL logic. (B) NAND logic.

Ans. (B)

Q.32 The time for which the D-input of a D-FF must not change after the clock is

applied is known as

(A) Hold time. (B) Set-up time.

Ans. (A)

Q.33 How many memory chips of (128 x 8) are needed to provide a memory

capacity of 4096 x 16?

(A)64 (B) A B

Ans. (A)

Q.34 In addition of two signed numbers, represented in 2' s complement form

generates an overflow if

(A) A. B = 0 (B) A = 0

Ans. (C)

Where A is the carry in to the sign bit position and B is the carry out of the

Sign bit position.

Q.35 Addition of (1111)2 to a 4 bit binary number 'a' results:-

(A) Incrementing A (B) Addition of (F)H

Ans. (C)

Q.36 In a microprocessor system, suppose. TRAP, HOLD, RESET Pin

got activated at the same time, while the processor was executing some

instructions, then it will first respond to

(A) TRAP (B) HOLD

Ans. (D)

Q.37 Pseudo instructions are

(A) Machine instructions (B) Logical instructions

Ans. (A)

Q.38 An attempt to access a location not owned by a Program is called

(A) Bus conflict (B) Address fault

Ans. (B)

Q. 39 Dynamic RAM consumes ________ Power and ________ then the Static RAM.

(A) more, faster (B) more, slower

Ans. (C)

Q.40 The flag register content after execution of following program by 8085

microprocessor shall be

Program

SUB A

MVI B, (01)H

DCR B

HLT

(A) (54)H (B) (44)H

Ans. (A)

Q.41 Which flag of the 8085's flag register is not accessible to programmer

directly?

(A)Zero flag

(B)Carry flag

(C)Auxiliary carry flag

(D)Parity flag

Ans. (C)

Q.42 Cache memory works on the principle of

(A) Locality of data.

(B) Locality of reference

(D) Locality of reference & memory

Ans. (B)

Q.43 Which of the following is a Pseudo instruction?

(A) SPHL (B) LXI

Ans. (D)

Q.44 A demultiplexer can be used as

(A)Encoder (B)Decoder

(C)Multiplexer (D)None of the above

Ans. (B)

Q.45 Excess-3 equivalent representation of (1234)H is

(A) (1237)Ex-3 (B) (4567)Ex-3

Ans. (B)

Q.46 Which of the memory holds the information when the Power Supply is switched

off?

(A) Static RAM (B) Dynamic RAM

Ans. (C)

Q.47 Minimum no. of NAND gate required to implement a Ex-OR function is

(A)2 (B)3

Ans. (C)

Q.48 Which of the following interrupt is maskable?

(A)INTR (B)RST 7.5

(C)TRAP (D)Both (A) and (B)

Ans. (B)

Q.49 Which of the following expression is not equivalent to x?

(A) x NAND x (B) x NOR x

Ans. (D)

Q.50 Word 20 contains 40

Word 30 contains 50

Word 40 contains 60

Word 50 contains 70

Which of the following instructions does not, load 60 into the Accumulator

(A) Load immediate 60

(B) Load direct 30

(D) both (A) & (C)

Ans. (B)

Q.51 An interrupt for which hardware automatically transfers the program to a specific

memory location is known as

(A) Software interrupt

(B) Hardware interrupt

(D) Vector interrupt

Ans. (B)

Q.52 Synchronous means _______

(A) At irregular intervals

(B) At same time

(D) None of these

Ans. (B)

Q.53 'n' Flip flops will divide the clock frequency by a factor of

(A)n2 (B) n

Ans. (B)

Q.54 In DMA the data transfer is controlled by

(A)Microprocessor (B) RAM

(C)Memory (D) I/O devices

Ans. (D)

Q.55 The number of instructions needed to add a numbers an store the result in memory

using only one address instruction is

(A)n (B) n - 1

(C)n +1 (D) Independent of n

Ans. (D)

Q.56 Negative numbers cannot be represented in

(A)Signed magnitude form

(B)I's complement form

(D)8-4-2-1 code

Ans. (C)

Q.57 Which of the following architecture is/are not suitable for realizing SIMD

(A)Vector Processor (B) Array Processor

(C)Von Neumann (D) All of the above

Ans. (C)

Q.58 In Boolean expression A+BC equals

(A)(A+B)(A+C) (B) (A'+B)(A'+C)

(C)(A+B)(A'+C) (D) (A+B)C

Ans. (A)

Q.59 A JK flip-flop can be implemented using D flip-flop connected such that

(A)D=JQ+KQ (B) D=JQ+KQ

(C)D=JQ+KQ (D) D=JQ+KQ

Ans. (A)

Q.60 An effective solution to the power consumption problem lies in using _______

transistors to implement ICs.

(A) NMOS (B) TTL shottky

Ans. (D)

Q.61 Memory interleaving technique is used to address the memory modules in order to

have

(A) higher average utilization

(B) faster access to a block of data

(D) both (A) & (B)

Ans. (C)

Q.62 In a multiprogramming system, which of the following is used

(A) Data parallelism (B) Paging concept

Ans. (B)

Q.63 Cycle stealing technique is used in

(A) Interrupt based data transfer

(B) Polled mode data transfer

(D) None of these

Ans. (C)

Q.64 Manipulation of individual bits of a word is often referred to as

(A) Bit twidding (B) Bit swapping

Ans. (A)

Q.65 Which of the following is not a characteristic of a RISC architecture.

(A) Large instruction set (B) One instruction per cycle

Ans. (A)

Q.66 When CPU is not fully loaded, which of the following method of data transfer is

preferred

(A) DMA (B) Interrupt

Ans. (D)

Q.67 Associative memory is some times called as

(A) Virtual memory (B) Cache memory

Ans. (D)

Q.68 BCD equivalent of Two's complement is

(A) nine's complement (B) ten's complement

Ans. (C)

Q.69 PAL circuit consists of

(A) Fixed OR & programmable AND logic

(B) Programmable OR & Fixed AND Logic

(D) Programmable OR & programmable AND logic

Ans. (A)

Q.70 8085 microprocessor carryout the subtraction by

(A) BCD subtraction method

(B) Hexadecimal subtraction method

(D) Floating Point subtraction method

Ans. (C)

Q.71 CPU checks for an interrupt signal during

(A) Starting of last Machine cycle

(B) Last T-State of instruction cycle

(D) Fetch cycle

Ans. (B)

Q.72 During DMA acknowledgement cycle, CPU relinquishes

(A) Address bus only (B) Address bus & control bus

Ans. (D)

Q.73 If the clock input applied to a cascaded Mod-6 & Mod-4 counter is 48KHz. Than

the output of the cascaded arrangement shall be of

(A) 4.8 KHz (B) 12 KHz

Ans.(C)

Q.74 If the stack pointer is initialised with (4FEB)H, then after execution of Push

operation in 8085 microprocessor, the Stack Pointer shall be

(A) 4FEA (B) 4FEC

Ans. (D)

Q.75 A more efficient way to organise a Page Table is by means of an associative

memory having

(A) Number of words equal to number of pages

(B) Number of words more than the number of pages

(D) Any of the above

Ans. (A)

Q.76 If there are four ROM ICs of 8K and two RAM ICs of 4K words, than the address

range of Ist RAM is (Assume initial addresses correspond to ROMs)

(A) (8000)H to (9FFF)H (B) (6000)H to (7FFF)H

Ans. (C)

Q.77 AÅBÅC is equal to A B C for

(A) A=0, B=1, C=0 (B) A=1, B=0, C=1

Ans. (D)

Q.78 Gray code equivalent of (1000)2 is

(A) (1111)G (B) (1100)G

Ans. (A)

Computer Architecture-2 Marks Question and Answers

PART A

1.Define Computer Architecture

Computer Architecture Is Defined As The Functional Operation Of The Individual H/W Unit In A Computer System And The Flow Of Information Among The Control Of Those Units

2.Define Computer H/W

Computer H/W Is The Electronic Circuit And Electro Mechanical Equipment That Constitutes The Computer

3. What Is Meant By Cache Memory ?

A Memory That Is Smaller And Faster Than Main Memory And That Is Interposed Between The Cpu And Main Memory. The Cache Acts As A Buffer For Recently Used Memory Location

4.what is locality of reference?

Many instruction in localized area of the program are executed repeatedly during some time period and the remainder of the program is accessed relatively infrequently .this is referred as locality of reference.

5.what is IO mapped input output? OR What is isolated I/O?,What is I/O Mapped I/O?

A memory reference instruction activated the READ M (or)WRITE M control line and does not affect the IO device. Separate IO instruction are required to activate the READ IOand WRITE IO lines ,which cause a word to be transferred between the address aio port and the CPU. The memory and IO address space are kept separate.

6.specify the three types of the DMA transfer techniques?

Single transfer mode(cyclestealing mode)

Block Transfer Mode(Brust Mode)

Demand Transfer Mode

Cascade Mode

7. why is memory refreshing circuit needed ?

al cells on the corresponding yow to be read and refreshed during both read and write operation .the contents of the d ram are maintained each row of cell must be accessed periodically once every 2 – 16 ms. refresh circuit usually performs this function .

automatically

8 what are the functions of control unit ?

the memory arithmetic and logic ,and input and output units store and process information and perform i/p and o/p operation, the operation of these unit must be co ordinate in some way this is the task of control unit the cu is effectively the nerve center that sends the control signal to other units and sence their states.

9.What is an interrupt?

An interrupt is an event that causes the execution of one program to be suspended and another program to be executed.

10.What are the uses of interrupts?

Recovery from errors
Debugging
Communication between programs
Use of interrupts in operating system

11.Define vectored interrupts.

In order to reduce the overhead involved in the polling process, a device requesting an interrupt may identify itself directly to the CPU. Then, the CPU can immediately start executing the corresponding interrupt-service routine. The term vectored interrupts refers to all interrupt-handling schemes base on this approach.

12. What is the need for reduced instruction chip?

1. Relatively few instruction types and addressing modes.

2. Fixed and easily decoded instruction formats.

3. Fast single-cycle instruction execution.

4. Hardwired rather than microprogrammed control.

13. Name any three of the standard I/O interface.

1. SCSI (small computer system interface),bus standards

2. Back plane bus standards

3. IEEE 796 bus (multibus signals)

4. NUBUS

5. IEEE 488 bus standard

14. Differentiate between RISC and CISC

RISC CISC

1. Reduced Instruction Set Computer 1. Complex Instruction set computer

2. Simple instructions take one cycle per 2. Complex instruction take multiple

Operation. Cycles per operation.

3. Few instructions and address modes are 3. Many instruction and address

Used. Modes.

4. Fixed format instructions are used. 4. Variable format instructions are

used.

5.Instructions are compiled and then 5. Instructions are interpreted by the

executed by hardware. Microprogram and then executed.

6. RISC machines are multiple register 6. CISC machines use single register

set. Set.

7. Complexity in the compiler 7. Complexity in the microprogram

8. RISC machines are higly piplined 8. CISC machines are not piplined.

15.Explain the pipeline types.

Instruction pipeline
Arithmetic pipeline

16. Explain the various classifications of parallel structures.

1. SISD (single instruction stream single data stream

2. SIMD(single instruction stream multiple data stream

3. MIMD(multiple instruction stream multiple data stream

4. MISD(multiple instruction stream single data stream

17. What is absolute addressing mode?

The address of the location of the operand is given explicitly as a part of the instruction.

Eg. Move a , 2000

18. Specify three types of data transfer techniques.

1. Arithmetic data transfer

2. Logical data transfer

3. Programmed control data transfer

19. What is the role of MAR and MDR?

The MAR (memory address register) is used to hold the address of the location to or from which data are to be transferred and the MDR(memory data register) contains the data to be written into or read out of the addressed location.

20. What are the various types of operations required for instructions?

1. Data transfers between the main memory and the CPU registers

2. Arithmetic and logic operation on data

3. Program sequencing and control

4. I/O transfers

21. What is the role of IR and PC?

Instruction Register (IR) contains the instruction being executed. Its output is available to the control circuits, which generate the timing signals for controlling the processing circuits needed to execute the instructions.

The Program Counter (PC) register keeps track of the execution of the program. It contains the memory address of the instruction currently being executed . During the execution of the current instruction, the contents of the PC are updated to correspond to the address of the next instructions to be executed.

22.Define memory access time?

The time that elapses between the initiation of an operation and completion of that operation ,for example ,the time between the READ and the MFC signals .This is

Referred to as memory access time.

23. Define memory cycle time.

The minimum time delay required between the initiations of two successive memory operations, for example, the time between two successive READ operations.

24.Define Static Memories.

Memories that consist of circuits capable of retaining the state as long as power is applied are known as static memories.

25.Distinguish Between Static RAM and Dynamic RAM?

Static RAM are fast, but they come at high cost because their cells require several transistors. Less expensive RAM can be implemented if simpler cells are used. However such cells do not retain their state indefinitely; Hence they are called Dynamic RAM.

26.Distiguish between asynchronies DRAM and synchronous RAM.

The specialized memory controller circuit provides the necessary control signals, RAS And CAS ,that govern the timing. The processor must take into account the delay in the response of the memory. Such memories are referred to as asynchronous DRAMS.

The DRAM whose operations is directly synchronized with a clock signal. Such

Memories are known as synchronous DRAM

27.what are the various units in the computer?

1,input unit

2.output unit

3.control unit

4.memory unit

5.arithmetic and logical unit

28.what is an I/O channel?

An i/o channel is actually a special purpose processor, also called peripheral processor.

The main processor initiates a transfer by passing the required information in the input output channel. the channel then takes over and controls the actual transfer of data.

29.what is a bus?

A collection of wires that connects several devices is called a bus.

30.Define word length?

Each group of n bits is referred to as a word of information and n is called the word length.

31.explain the following the address instruction?

1.three-address instruction-it can be represented as

add a,b,c

Operands a,b are called source operand and c is called destination operand.

2.two-address instruction-it can be represented as

add a,b

3.one address instruction-it can be represented as

add a

4.1 1/2 address instruction

it can be represented the type of instruction in which one address always refers to a location in the main memory and the other, shorter address always refers to a cpu register, is intermediate to the one-two-address formats because of this property is called I ½ address format.

5.zero address instruction.

It is also possible to use instruction where the location s of all operand are defined implicitly. This operand of the use of the method for storing the operand in which called push down stack. Such instructions are sometimes referred to us zero address instruction.

32.what is the straight-line sequencing?

the cpu control circuitry automatically proceed to fetch and execute instruction, one at a time in the order of the increasing addresses. This is called straight line sequencing.

33.what is the role of pc?

The cpu contains a register called the program counter, which holds the address of instruction to be executed next.. to begin the execution of the program the address of its

First instruction must be placed into the pc.

34.what are steps for execution of a complete instruction?

1.fetch the instruction.
2.fetch the first operand (the contents of the memory location pointed by the address field of the instruction.)

3.perform the calculation.

4.load the result.

35.what is a a bit slice?

A bit slice is “slice” through the data path of the typical processor. It contains all

Circuits necessary to provide alu function, register transfer and control function for only a few bits of the data path.

36.what is DMA?

A special control unit may be provided to enable transfer a block of data directly between an external device and memory without contiguous intervention by the cpu. This approach is called DMA.

37.why program controlled I/O is unsuitable for high-speed data transfer?

in program controlled i/o considerable overhead is incurred.. because several program instruction have to be executed for each data word transferred between the external devices and MM.
many high speed peripheral; devices have a synchronous modes of operation.

that is data transfer are controlled by a clock of fixed frequency, independent of the cpu.

38.what is the function of i/o interface?

The function is to coordinate the transfer of data between the cpu and external devices.

39.what is NUBUS?

A NUBUS is a processor independent, synchronous bus standard intended for use in

32 bit micro processor system. It defines a backplane into which upto 16 devices may be plugged each in the form of circuit board of standard dimensions.

40. what do you mean associative mapping technique?

The tag of an address received from the CPU is compared to the tag bits of each block of the cache to see if the desired block is present. This is called associative mapping technique.

41. What is LRU replacement algorithm?

When a block is to be overwritten it is sensible to overwrite the one that has gone the largest time without being referenced. This block is called Least Recently Used block and the technique is called LRU replacement algorithm.

42. Explain virtual memory technique.

Techniques that automatically move program and data blocks into the physical memory when they are required for execution are called virtual memory technique.

43. What are virtual and logical addresses?

The binary addresses that the processor issues for either instruction or data are called virtual or logical addresses.

44. Define translation buffer.

Most commercial virtual memory systems incorporate a mechanism that can avoid the bulk of the main memory access called for by the virtual to physical addresses translation buffer. This may be done with a cache memory called a translation buffer, which retains the results of the recent translation.

45. Name some of the IO devices.

1. Video terminals

2. Video displays

3. Alphanumeric displays

4. Graphics displays

5. Flat panel displays

6. Printers

7. Plotters

46. What is branch delay slot?

The location containing an instruction that may be fetched and then discarded because of the branch is called branch delay slot.

47. What is optical memory?

Optical or light based techniques for data storage, such memories usually employ optical disk which resemble magnetic disk in that they store binary information in concentric tracks on an electromechanically rotated disks. The information is read as or written optically, however with a laser replacing the read write arm of a magnetic disk drive. Optical memory offer high storage capacities but their access rate is are generally less than those of magnetic disk.

48. What is microprogrammed control?

Microprogrammed control in which control signals are generated by a program similar to machine language program. A sequence of one (or) more microoperation, such as addition, multiplication is called a micro program. The address where these microinstructions are stored in CM is generated by microprogrammed control.

49. What is microprogramming?

A sequence of Control Words corresponding to the control sequence of a machine instruction constitutes the micro routine for that instruction, and the individual control words in this micro routine are referred to as microinstructions.

Microprogramming is a method of control unit design in which the control signal selection and sequencing information is stored in a ROM (or) RAM called a control memory CM.

50.What are static and dynamic memories?

Static memory are memories which require periodic no refreshing. Dynamic memories are memories, which require periodic refreshing.

51. What are the steps required for a pipelinened processor to process the instruction?

1. F Fetch: read the instruction from the memory

2. D Decode: decode the instruction and fetch the source operand(s).

3. E Execute: perform the operation specified by the instruction.

4. W Write: store the result in the destination location.

52. What are the steps taken when an interrupt occurs?

1. Source of the interrupt

2. The memory address of the required ISP

3. The program counter & cpu information saved in subroutine

4. Transfer control back to the interrupted program

53 Define instruction pipeline.

The transfer of instructions through various stages of the cpu instruction cycle., including fetch opcode,decode opcode,compute operand addresses. Fetch operands, execute instructions and store results. This amounts to realizing most (or) all of the cpu in the form of multifunction pipeline called an instruction pipelining.

54. Define latency.

The term memory latency is used to refer to the amount of time it takes to transfer a word of data to or from the memory. The term latency is used to denote the time it takes to transfer the first word of data. This time is usually substantially longer than the time needed to transfer each subsequent word of a block.

55. Define bandwidth.

Bandwidth is a product of the rate at which the data are transferred (and accessed) and the width of the data bus.

56. Define hit rate.

A successful access to data in a cache is called a hit. Number of hits stated as a fraction of all attempted accesses is called the hit rate.

57. Define miss rate.

A miss rate is the number of misses stated as a fraction of attempted accesses. Extra time needed to bring the desired information into the cache is called the miss penalty.

58. Distinguish between system space and user space.

assembling the operating system routine into a virtual address space , is called system space that is separate from the virtual space in which user application program reside. The latter space is called user space.

59.Define

1. Signal - The binary information is represented in digital computers by physical quantities called signals.

Gates – The manipulation of binary information is done by logic circuits called gates. Gates are blocks of hardware that produce signals of binary 1 or 0 where input logic requirements are satisfied.

3. Flip flop – The storage elements employed in clocked sequential circuits are called flip flops. A flip flop is a binary cell capable of storing 1 bit of information.

60. Define combinational circuit.

A combinational circuit is a connected arrangement of logic gates with the set of inputs and outputs. A combinational circuit transforms binary information from the given input data to the required output data. Combinational are employed in digital computers required for generating binary control decisions and for providing digital components required for data processing.

61. Define sequential circuits.

A sequential circuit is an interconnectin of flip-flops and gates. The gates by themselves constitute a combinational circuit, but when included with the flip flops, the overall circuit is classified as a sequential circuit.

62. Define interface.

The word interface refers to the boundary between two circuits or devices.

63. Define pipelining.

Pipelining is a techinique of decomposing a sequential process into sub operations with each subprocess being executed in a special dedicated segment that operates concurrently with all other segments.

64. Define parallel processing.

Parallel processing is a term used to denote a large class of techniques that are used to provide simultaneous data-processing tasks for the purpose of increasing the computational speed of a computer system. Instead of processing each instruction sequentially as in a conventional computer, a parallel processing system is able to perform concurrent data processing to achieve faster execution time.

65. What are the components of memory management unit?

A facility for dynamic storage relocation that maps logical memory references into physical memory addresses.

2 A provision for sharing common programs stored in memory by different users .

.3. Protection of information against unauthorized access between users and preventing users from changing operating system functions.

66. What is programmed I/O?

Data transfer to and from peripherals may be handled using this mode. Programmed I/O operations are the result of I/O instructions written in the computer program.

67. Define Memory interleaving ?

In Memory interleaving, memory is divided into several modules and the technique is used to address the memory modules in order to have reduced complexity in mapping hardware